INSPECT

Intra Node Stencil Performance Evaluation Collection

Stencil Properties

dimension 3D
radius 1
weighting homogeneous
kind box
coefficients variable
datatype double
machine HaswellEP_E5-2695v3_CoD
FLOP per LUP 27
flavor Cluster on Die

Data has been reviewed

Julian Hornich says:

Level two (L2) cache bandwidth is optimistic, may be up to 64 B/cy as stated by Intel. But in practice this value is rarely reached.


Benchmark raw data shown on this page can be found in the according folder of the git repository.

If you have feedback, issues or found errors on this page, please submit an issue on the github page.

Kernel Source Code

double a[M][N][P];
double b[M][N][P];
double W[1][M][N][P];

for (int k = 1; k < M - 1; ++k) {
  for (int j = 1; j < N - 1; ++j) {
    for (int i = 1; i < P - 1; ++i) {
      b[k][j][i] =
          W[0][k][j][i] *
          (a[k][j][i] + a[k - 1][j - 1][i - 1] + a[k][j - 1][i - 1] +
           a[k + 1][j - 1][i - 1] + a[k - 1][j][i - 1] +
           a[k][j][i - 1] + a[k + 1][j][i - 1] +
           a[k - 1][j + 1][i - 1] + a[k][j + 1][i - 1] +
           a[k + 1][j + 1][i - 1] + a[k - 1][j - 1][i] +
           a[k][j - 1][i] + a[k + 1][j - 1][i] + a[k - 1][j][i] +
           a[k + 1][j][i] + a[k - 1][j + 1][i] + a[k][j + 1][i] +
           a[k + 1][j + 1][i] + a[k - 1][j - 1][i + 1] +
           a[k][j - 1][i + 1] + a[k + 1][j - 1][i + 1] +
           a[k - 1][j][i + 1] + a[k][j][i + 1] + a[k + 1][j][i + 1] +
           a[k - 1][j + 1][i + 1] + a[k][j + 1][i + 1] +
           a[k + 1][j + 1][i + 1]);
    }
  }
}

Layer Conditions

1D Layer Condition:

  • L1: unconditionally fulfilled
  • L2: unconditionally fulfilled
  • L3: unconditionally fulfilled

2D Layer Condition:

  • L1: P <= 4100/11, that is P <= 370
  • L2: P <= 32772/11, that is P <= 2970
  • L3: P <= 2359300/11, that is P <= 214480

3D Layer Condition:

  • L1: 40*N*P - 32*P - 32 <= 32768, that is N*P <= 20²
  • L2: 40*N*P - 32*P - 32 <= 262144, that is N*P <= 80²
  • L3: 40*N*P - 32*P - 32 <= 18874368, that is N*P <= 680²

Have a look at the kernel source code for dimension naming.

How to test this stencil

Generate this stencil with:

stempel gen -D 3 -r 1 -t "double" -C variable -k box -o --store stencil.c

and generate the compilable benchmark code with:

stempel bench stencil.c -m HaswellEP_E5-2695v3_CoD.yml --store

Compiler flags

icc -O3 -xCORE-AVX2 -fno-alias -qopenmp -DLIKWID_PERFMON -Ilikwid-4.3.2/include -Llikwid-4.3.2/lib -Iheaders/dummy.c stencil_compilable.c -o stencil -llikwid

Single Core Grid Scaling

ECM Prediction vs. Performance

Comparison of the measured stencil performance (in cycles per cache line), roofline prediction and the (stacked) contributions of the ECM Performance Model predicted by kerncraft using Layer Conditions to model the cache behavior. The calculated layer conditions shown above correspond to the jumps in the ECM prediction in this plot.

Data Transfers between Caches

Data transfers between the different cache levels and main memory. The shown data for each level contains evicted and loaded data. The measured data is represented by points and the predicted transfer rates by kerncraft by lines.

Review status: Data has been reviewed

Multi Core Thread Scaling

Something is wrong...

Julian Hammer says:

faulty measurement


Single Core Spatial Blocking

Something is wrong...

Julian Hammer says:

missing blocked measurements


How to replicate this data

Single Core Measurements

Using the generated stencil and kerncraft, all single core performance data shown on this page can be reproduced by:

Layer Condition Data

kerncraft -p ECM -p RooflineIACA -p Benchmark -p LC -P LC -m HaswellEP_E5-2695v3_CoD.yml stencil.c -D N $GRID_SIZE -D M $GRID_SIZE -D P $GRID_SIZE -vvv --cores 1 --compiler icc

Cache Simulator Data

kerncraft -p ECM -p RooflineIACA -p Benchmark -p LC -P CS -m HaswellEP_E5-2695v3_CoD.yml stencil.c -D N $GRID_SIZE -D M $GRID_SIZE -D P $GRID_SIZE -vvv --cores 1 --compiler icc

Thread Scaling Measurements

The generated benchmark code can be used to reproduce the thread scaling data shown on this page by:

kerncraft -p ECM -p RooflineIACA -p Benchmark -P LC -m HaswellEP_E5-2695v3_CoD.yml stencil.c -D N $GRID_SIZE -D M $GRID_SIZE -D P $GRID_SIZE -vvv --cores $CORES --compiler icc

The roofline prediction can be obtained with kerncraft and the generated stencil:

kerncraft -p RooflineIACA -P LC -m HaswellEP_E5-2695v3_CoD.yml stencil.c -D N $GRID_SIZE -D M $GRID_SIZE -D P $GRID_SIZE -vvv --cores ${threads} --compiler icc

Spatial Blocking Measurements

Generate benchmark code from the stencil with blocking and compile it as shown before:

stempel bench stencil.c -m HaswellEP_E5-2695v3_CoD.yml -b 2 --store

OMP_NUM_THREADS=1 likwid-pin -C S0:0 ./stencil $GRID_SIZE $GRID_SIZE $GRID_SIZE $BLOCKING_M $BLOCKING_N $BLOCKING_P